The Design of an SRAM - BasedField - Programmable

101 The Design of an SRAM-Based Field-Programmable Gate Array, Part II: Circuit Design and Layout Paul Chow, Soon Ong Seo, Jonathan Rose, Kevin Chung, Gerard P aez-Monz on and Immanuel Rahardja Abstract|Field-Programmable Gate Arrays (FPGAs) are now widely used for the implementation of digital systems and many commercial architectures are available. Although the literature and data books contain detailed descriptions of these architectures, there is very little information on how the high-level architecture was chosen and no information on the circuit-level or physical design of the devices. In Part I, we described the high-level architectural design of an SRAM-programmable FPGA. This paper, Part II, will address the circuit design issues through to the physical layout. We consider area-speed trade-o s in the design of the logic block circuits and in the connections between the logic and the routing structure. All commercial FPGA designs are done using full-custom hand layout to obtain absolute minimum die sizes. This is both labor and time-intensive. We propose a design style with a mini-tile that contains a portion of all the components in the logic tile, resulting in less full-custom e ort. The mini-tile is replicated in a 4 4 array to create a macro tile. The mini-tile is optimized for layout density and speed, and is customized in the array by adding appropriate vias. This technique also permits easily changing the hard-wired connections in the logic block architecture, and the segmentation length distribution in the routing architecture. Keywords| eld-programmable gate arrays, FPGA, FPGA architecture, SRAM programmable, FPGA circuit design